1. Technical Field
This invention relates in general to disk storage devices and, more particularly, to a high speed preamplifier/write driver.
2. Description of the Related Art
Almost all business and home computers use a hard disk drive storage system for mass storage requirements. A hard disk drive stores data by individually modifying the magnetic orientation of small regions of a disk surface. As shown in FIG. 1, a hard disk drive 10 typically includes one or more rotating disks 12. A head assembly 14 associated with each surface of the disks 12 typically includes separate read and write heads for reading data from the disk and writing data to the disk. The write head is essentially a small coil of wire which stores data by magnetizing small regions along a disk's tracks. A current driven through the write head in a first direction magnetizes a small region of the disk under the head at a first orientation and a current driven through the write head in the opposite direction magnetizes a small region of the disk under the head at a second orientation. The read head distinguishes the magnetic orientation of each bit location to derive logical “1s” and “0s”.
The circuit which drives the write head is referred to as a “write driver”, which is part of the read/write preamplifier 16. The write driver controls the direction of the flow of current through the head, responsive to information from the channel circuitry 18. The channel circuitry receives data from the hard drive controller 20 of the computer 22. The computer 22 further includes processing circuitry and other components (not shown).
A recent requirement from disk drive manufacturers is that the preamplifier write driver provides a symmetric write driver signal for reduced noise coupling. A symmetric write driver must have equal and opposite positive and negative write driver signals over all frequency data patterns. These write driver signals must be symmetric in amplitude as well as transient behavior. If the positive and negative write driver signals are well matched in amplitude and transient behavior, the write driver will have virtually no common-mode signal component. The requirement of a symmetrical write driver is driven by read head reliability as the new generation of magneto-resistive (MR) heads is much more sensitive to capacitive coupling from the write driver. Non-symmetrical write drivers with large common-mode voltage components can capacitively couple damaging voltage levels, both differentially and single-ended, to the read head. Generally symmetrical write drivers have been developed to address this problem.
Write drivers drive the write head differentially to achieve the maximum voltage possible across the write head for both positive and negative transitions. The requirement of driving the write head differentially means that both sides of the write driver must have bi-directional drive capability.
FIGS. 2a and 2b illustrate examples of typical prior art current-mode write drivers. Unlike voltage-mode write drivers, where an impedance match resistor can be placed in series with the low impedance output of the voltage drive device, current-mode write drivers must place the impedance match resistor in parallel with the high-impedance output of the current drive device. Traditionally, in symmetrical write drivers (with the common-mode output voltage kept near ground), the impedance match resistor has been placed either from each output node to ground through a capacitor or across the output nodes through a capacitor. The purpose of the capacitor is to prevent DC current from being stolen by the impedance match resistors.
These methods have two main drawbacks. First, a large amount of current is shunted away from the inductive write head load (connected between the output nodes) through the low-valued impedance match resistors during the overshoot or pulsing time period when the output voltages can swing near rail to rail (−5 v to +5 v). This current is essentially wasted since it is not being delivered to the write head, which increases power dissipation without increasing performance. Secondly, the capacitor must be sized somewhat large to realize a low impedance at frequencies of interest and provide effective impedance matching. This capacitance, along with the impedance match resistance, creates an RC pole that lies well within the write data frequency range. Thus, settling is not achieved. The corresponding RC decay adversely affects the write current waveshape and hurts performance. The capacitor therefore limits the maximum frequency of the write driver.
In FIG. 2a, the output ports OUTP and OUTN drive the inductive write head load 32. OUTP and OUTN are driven by the output devices Q0, Q1, Q2 and Q3. The symmetrical nature of an NPN differential pair (Q2–Q3) balanced by a PNP differential pair (Q0–Q1) provides the ability to keep the common-mode output voltage around ground over a high frequency pattern. Q0–Q3 are driven by the differential write data input voltages VTOPN, VTOPP, VBOTN, VBOTP. If VTOPP is at a lower potential than VTOPN and VBOTN is at a higher potential than VBOTP, then PNP transistor Q1 and NPN transistor Q2 will conduct, while PNP transistors Q0 and NPN transistor Q3 will not conduct. Accordingly, a current path is established from Vcc to Vee (as shown by the dotted line) through R5, Q1, head 32, Q2 and R3. Similarly, If VTOPN is at a lower potential than VTOPP and VBOTP is at a higher potential than VBOTN, then PNP transistor Q0 and NPN transistor Q3 will conduct, while PNP transistors Q1 and NPN transistor Q2 will not conduct. Accordingly, a current path is established from Vcc to Vee in the opposite direction through head 32. The write driver of FIG. 2b works in a similar fashion; the difference between the circuits of FIGS. 2a and 2b concerns the manner in which impedance matching is performed.
In FIG. 2a, impedance matching is provided by the impedance match resistors R0 and R1 (both having a value equal to half of the matching resistance) along with C0 and C1. In FIG. 2b, impedance matching is provided by the impedance match resistors R20 and R21 (both having a value equal to half of the matching resistance) along with C4. The DC voltage of both OUTP and OUTN, as well as the AC common-mode output voltage, is set around ground by R14 and R15 in FIG. 2a and by R16 and R17 in FIG. 2b. The value of these resistors is large compared to the impedance match resistors.
As mentioned above, the output voltages OUTP and OUTN can swing near rail to rail (−5 v to +5 v). Typical impedance match resistors are valued around 70 ohms differential. As an example, a differential output voltage swing of 8 v (which allows headroom for circuitry) during the overshoot phase placed across a differential match resistance of 70 ohms shunts 114 mA away from the write head load through the match resistors. This large amount of wasted current significantly increases power dissipation without any increase in performance.
Accordingly, a need has arisen for a balanced current-mode write driver with improved power efficiency and without an RC pole that limits the speed of the device.